1. Field of the Invention
This invention relates to the field of electronic devices, and in particular to memory devices.
2. Description of Related Art
Memory devices are commonly designed to be as small as possible, so as to maximize the storage density. Typically, as illustrated in FIG. 1, each memory element, or cell 180, comprises a pair of cross-coupled inverters 181, 182. The output of each inverter 181, 182 is connected to the input of the other inverter 182, 181, and connected to a bus 111, 110, to which other memory elements are also connected. Conventional selection means 170, such as "row" and "column" selection, connect the selected memory element 180 to the buses 110, 111. The output of one 182 of the inverters is connected to a "data" bus 110, and the output of the other inverter 181 is connected to a "data-not", or "data-bar", bus 111, each logic output value being opposite the other, due to this cross-coupling.
Typically, for maximum circuit density, the inverters 182, 181 are minimally sized, and are not able to provide sufficient power to bring the respective data 110 and data-not 111 buses to a true logic-zero or logic-one state. That is, they are insufficiently sized to sink or source the charge on the bus so that one of the busses is brought to a ground potential, and one of the busses is brought to the power supply potential, typically termed Vdd. Thus, a differential detector 190 is typically provided to sense a difference between the voltages on the data 110 and data-not 111 busses, and produces the appropriate logic output value 195 corresponding to the state of the memory element 180.
To properly detect the voltage differential presented at the data 110 and data-not 111 buses, the data 110 and data-not 111 buses are "precharged" to a known voltage before the particular memory cell 180 is connected to the buses. The known voltage is typically selected to be a voltage that is not sufficiently high, nor sufficiently low, to cause either inverter 181, 182 in the memory cell 180 to change state. FIG. 1 illustrates an example precharge circuit 100 that is commonly used to precharge the data 110 and data-not 111 lines to a voltage level that is approximately equal to half the supply voltage Vdd 101. FIG. 2 illustrates an example timing diagram corresponding to the operation of the circuit that is illustrated in FIG. 1.
The precharge circuit 100 comprises a pair of inverters 121, 122. The inverter 121 is formed by transistors P1 and N1, and has an input 130 and output 140. The inverter 122 is formed by transistors P2 and N2, and has an input 140 and an output 130. Thus, this inverter pair 121, 122 is similar in structure to the inverter pair 181, 182 a conventional memory cell 180. As contrast to a conventional memory cell 180, a switch transistor X3 is provided that, when enabled by signal PhA 150, illustrated by the pulse 201 on Line 2A of FIG. 2, connects the inputs and the outputs 130, 140 of the cross-coupled inverters 121, 122 together. When the inputs and outputs 130, 140 are connected, both inverters 121, 122 enter the active state, such that all four transistors P1, N1, P2, N2 are conducting. With all of the transistors P1, N1, P2, N2 conducting, the voltage at node 130 will go to the threshold voltage of the inverters, which is substantially equal to half the supply voltage Vdd, as illustrated at 231 on line 2D of FIG. 2. That is, the supply voltage Vdd is divided between the voltage drop across the p-channel transistors P1, P2, and the voltage drop across the n-channel transistors N1, N2, respectively.
In typical operation, after control signal PhA 150 is asserted to bring nodes 130 and 140 to half the supply voltage Vdd 101, the control signal PhB 160 is asserted, at 211 of Line 2B of FIG. 2. Signal PhB 160 controls switch transistors X1 and X2. When control signal PhB 160 is asserted, the voltage at node 130 is placed on both the data 110 and the data-not 111 buses, as illustrated at 241 of Line 2E of FIG. 2. Thereafter, the control signals PhA 150 and PhB 160 are de-asserted, at 202 and 212 of Lines 2A and 2B of FIG. 2, respectively. The capacitance associated with the buses 110 and 111 maintain each bus at the transferred voltage from node 130 (nominally Vdd/2). That is, the buses 110, 111 are precharged to the nominal voltage level of Vdd/2.
Having precharged each bus 110, 111 to the same voltage level, the particular memory cell, cell 180 in this example, is selected for a "read" of the value contained within the memory cell 180, as illustrated at 225 of Line 2C of FIG. 2. Because the memory cell 180 contains opposing inverters 181, 182, the voltage level on one of the buses 110, 111 increases while the voltage at the other bus 111, 110 decreases, depending upon the logic value stored in the cell 180, as determined by the state of the cross-coupled inverters 181, 182, and as illustrated at 245 of Line 2E of FIG. 2. This difference in voltage levels on the data 110 and data-not 111 buses is detected by the differential amplifier 190, and an appropriate logic-0 or logic-1 value is produced by the differential amplifier 190, corresponding to the logic state of the selected memory device 180, as illustrated at 255 of Line 2G of FIG. 2.
Note that, to produce the nominal reference voltage Vdd/2 for transfer to the data 110 and data-not 111 buses, at 231 of FIG. 2, the four transistors P1, N1, P2, N2 are placed in a conductive mode. During this conductive mode, current flows through the transistors P1, N1, P2, N2 from the voltage source Vdd 101. This current flow minimizes the effective utilization period for portable and hand-held computer devices, because this current is typically drawn from a battery source, with limited energy providing potential.